![]() ![]() However, it imposed a sizable performance hit. AMD was able to release a software patch to keep the TLB bug at bay. But a flaw in Barcelona (known as the TLB bug) could cause the CPU to lock up. The first K10 processors were based on the Barcelona configuration and sold as Opteron server processors. Unfortunately, the K10 ran into problems early on. IPC was improved compared to K8, but K10's greatest advantage was its quad-core design that enabled it to run laps around the K8 dual-core CPUs in heavily-threaded applications. It is closely related to the K8, but it had several enhancements to the core and associated cache and memory controller. Socket 754 (Venice)/ Socket 939 (Winchester and San Diego)ĪMD's next architecture, K10, was a rather ambitious design. Single-Channel 400 MHz DDR (Venice)/ Dual-Channel 400 MHz DDR (Winchester and San Diego)Ĩ00 MHz (Venice)/ 1000 MHz (Winchester and San Diego)Ħ4 W TDP (Winchester)/ 89 W TDP (Venice and San Diego) 2004 (Winchester)/2005 (Venice and San Diego)ĥ12 KB (Full Speed - Winchester and Venice)/ 1 MB (Full Speed - San Diego)ĥ12 KB (Full Speed - Orleans and Lima), 1 MB (Full Speed - Lima)ġ.8 - 2.2 GHz (Winchester)/ 1.8 - 2.4 GHz (Venice)/ 2.2 - 2.6 GHz (San Diego)ġ.8 - 2.6 GHz (Orleans)/ 2 - 2.8 GHz (Lima)
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